As device sizes and power requirements decrease, attempts are being made to improve the electron mobility in the channel region of metal-oxide semiconductor field-effect transistors (MOSFETs). One such attempt includes inducing strain in the channel region. It has been found that a strained channel region improves carrier mobility within the channel region. The magnitude of strain directly affects the amount of improvement or degradation to the carrier mobility and transistor performance.
An ideal strained channel transistor 10 is shown in FIG. 1a. The strained channel transistor 10 includes a gate structure 11 having a gate dielectric 14 underlying a gate electrode 16. The gate structure 11 also includes spacers 18 formed along the sidewalls of the gate electrode 16 and the gate dielectric 14. A material having a different lattice constant is formed in recessed regions 20. Because the material in the recessed regions 20 have a different lattice constant, a lattice mismatch occurs and induces a strain in the region of the substrate positioned between the recessed regions 20, e.g., the channel region. Ion implants may be performed to form lightly-doped drains 24 and heavily-doped source/drain regions 22.
Attempts have also varied the position of the recessed regions 20. For example, the recessed regions 20 may be formed in the LDD 24 and the heavily-doped source/drain regions 22 as illustrated in FIG. 1a. Other attempts form the recessed regions 20 in the heavily-doped source/drain regions 22 as illustrated in FIG. 1b. Yet other attempts (not shown) may utilize dummy spacers to position the recessed regions under a portion of the spacers 18.
Strained channel manufacturing techniques, however, frequently comprise steps that may damage the gate structure 11, contributing to degraded transistor performance. For example, the recessed regions 20 are typically formed by a silicon etching step performed after the gate dielectric 14 and the gate electrode 16 have been formed. After the silicon etching step is performed, a material having a lattice mismatch with the underlying substrate is grown. Silicon germanium is frequently used to form the recessed regions when a silicon substrate is used. Exposing the gate structure 11 to the silicon etching steps may damage the gate structure 11 and adversely affect the performance of the transistor.
Furthermore, some attempts, such as that illustrated in FIG. 1b, perform the silicon etching steps after the formation of the spacers 18. In these attempts, the silicon etching process may also erode the spacers 18, as illustrated by the spacers being etched below the top of the gate electrode 16 in FIG. 1b. The eroded thickness and height of spacers 18 after the silicon etch back step provide less protection and isolation to the gate structure 11 and may expose the gate electrode 16 to cracks 25 (FIG. 1b) in an overlying dielectric layer (not shown), such as an etch stop layer or an inter-level dielectric layer, possibly leading to short-circuiting and transistor malfunction.
Furthermore, the gate structure 11 may also be exposed to a hydrofluoric acid or other cleaning solutions applied during a pre-cleaning process performed before depositing the lattice mismatch material. The pre-cleaning process may result in spacer voids 28, shown in FIG. 1b, wherein the oxide liner 32 below the spacers 18 is partially etched. The spacer voids may cause silicide formation under the spacers and may cause the spacer to peel.
Another issue may arise as a result of a wafer pre-bake step that is commonly performed before SiGe deposition. The pre-bake step may include heating the wafer to 850° C. or more for five minutes or more before the lattice mismatch material is deposited. This pre-bake step lowers the thermal budget available for LDD implant annealing, source/drain implant annealing, and other manufacturing steps requiring high temperatures, thereby unnecessarily imposing restrictions on other processing steps.
FIG. 1b also illustrates a mushroom-like shape 30 that may be formed over the gate structure 11. The mushroom-like shape 30 is a common and undesired result of exposing the gate structure 11 to the SiGe deposition step. The mushroom-like shape 30 may adversely affect the characteristics of the transistor.